Those who are interested to learn VHDL and start their career as a SOC Verification Engineer. Topics Covered Introduction to VHDL- Basic Language elements-Behavioral Modelling-Dataflow Modeling-Structural modeling-Generics and Configurations-Subprograms and Overloading-Package and Libraries-Model Simulation.

Syllabus(Basic Level) ********** Overview of C (1hour) Constants. Variables and Data Types(1hour) Operators and Expressions(2hour) Managing Input and Output -Operations.(2hour) Decision Making and Branching.(2hour) Decision making and Looping(2hour) Advanced Topics ******************* Arrays(3hour) Character Arrays and Strings(2hour) User-defined Functions(3hour) Structures and Unions(3hour) Pointers(3hour) File handling(3hour) Linked list(3hour) The preprocessor(1hour) Total course duration: